

ABSTRACT

Apparatus and method for testing complex electronic circuitry including in particular solid state semiconductor devices. Generation of worst case stressing patterns for the testing of Large Scale Integration devices is accomplished by varying the values of the &#34;ones&#34; and &#34;zeros&#34; of a test pattern impressed on the device under test. All or any portion of the &#34;ones&#34; are either at a &#34;Most Positive UP Level&#34; (M.P.U.L.) or at a &#34;Least Positive UP Level&#34; (L.P.U.L.). Correspondingly all or any portion of the &#34;zeros&#34; are either at a &#34;Least Negative Down Level&#34; (LNDL) or at a &#34;Most Negative Down Level&#34; (MNDL).



